The downsizing and lightening of the electronic equipment are requested. Especially, in a small satellite, it is strongly required to achieve high functionality, high performance, downsizing and lightening of a satellite while maintaining the size of the satellite. Therefore, it is necessary to further carry out downsizing and high density mounting even in an electronic device such as an information processing apparatus mounted in the satellite. It is possible to cope with the downsizing of the information processing apparatus to an extent by the technique such as SOC (System On Chip), HIC (Hybrid IC), and MCM (Multi-Chip Module).
FIG. 1 is a side view schematically showing a configuration example of a conventional MCM. The MCM 101 contains a mount substrate 110, an IC package 111, an IC package 112 and wiring lines 113. The IC package 111 and the IC package 112 contain a semiconductor chip 121 and a semiconductor chip 122, respectively. The mount substrate 110 is a circuit board made from ceramic or resin. For example, the semiconductor chips 121 and 122 are each exemplified by a CPU, a memory, and a sensor. The wiring lines 113 provided inside the substrate 110 and on the surface of the substrate 110 connect the IC packages 111 and 112 and other electronic devices. In this case, the line width of the wiring line 113 is wide (the minimum width of about 200 μm) and it needs to secure an area necessary for the wiring lines. Therefore, the substrate 110 cannot be made small. For this reason, it is difficult that the downsizing and lightening of the MCM 101 are dealt with.
As the related techniques, in JP 2012-529770A (WO2010/151350) discloses a method of providing a multichip package and inter-connection from a die to a die in the multichip package. The multichip package contains a substrate, a first die, a second die and a bridge. The substrate has a first surface, a second surface opposite to it, and a third surface extending from the first surface to the second surface. The first die and the second die are mounted on the first surface of the substrate. The bridge is mounted on the first die and the second die adjacent to the third surface of the substrate. Any part of the substrate does not exist under the bridge. The bridge connects the first die and the second die.
In this prior art, there is a case that the second die is mounted on the first die mounted on the substrate (there is a case that the bridge is the die). In such a case, the wiring line of the second die mounted on the upper side needs to pass through the first die mounted on the lower side. Therefore, it would be a restriction of height when mounting the dies in a height direction.
The technique of room-temperature bonding which can bond semiconductor substrates at the normal temperature is disclosed in Japanese Patent 2,791,429B, Japanese Patent 3,970,304B and JP 2003-318219A.